Radiation hardened by design technique to mitigate single event transients in combinational logic circuits

Single event transients (SETs) have become increasingly problematic for both combinational and sequential VLSI circuits in the deep submicron technology (DSM). This is due to continuously decreasing feature sizes, lower supply voltages and higher operating frequencies. Many critical applications such as biomedical, space and military electronics as well as several mainstream computing applications demand reliable circuit functionality. Therefore, the circuits used in these application must be tolerant to SEU/SET events and therefore, these circuits are designed using circuit hardening approaches. Hardening by design techniques based on increasing the amount of charge representing the bit and redundancy techniques have been used over the years. In this paper, we present a novel design strategy to reduce the impact of radiation-induced single event transients (SET) on combinational logic circuits. It presents a Radiation Hardened By Design (RHBD) of combinational circuits using 0.18μm technology and developed with the help of Cadence tool. This design style achieves SET mitigation by using C element and strengthening the sensitive output node. In order to check the accuracy of our proposal, we compare it with others techniques for hardening radiation at the transistor level against a single event transient. Simulation results show that the proposed method has a good soft error tolerance capability with minimum area, power and speed penalties.