Patterning challenges in 193i-based tip to tip in N5 interconnects

CMOS area scaling to N5 dimensions will have interconnect metal pitch around 30nm. Patterning such small features, using 193 ArF immersion lithography (193i), is only possible with pitch multiplication techniques such as SADP, SAQP, SAOP, etc. An additional keep or block patterning process is often used to achieve line interruptions and turns essential to have functional electrical devices. In this paper, we review three block patterning approaches experimented on imec's 32nm metal pitch N5 test vehicles. We discuss the merits and challenges of each patterning option and describe, qualitatively, process interactions with lithography parameters such as alignment and overlay. Lastly, we show that EUV block approach is a simpler benchmark in terms of process complexity and cost.