An optimized hardware implementation of 4-point adaptive multiple transform design for post-HEVC

Under the exploration of the future video coding standard, a new transform design called Adaptive Multiple Transform (AMT) has been proposed. It involves five DCT/DST-based transform types known as: DCT-II, DCT-VIII, DCT-V, DST-I and DST-VII. This work, proposes multiplierless hardware architectures of size 4 for all considered transform types. These architectures are implemented in FPGA benefitting from both correlation and symmetry properties of the matrices coefficients. This paper presents and compares two different architecture aspects without and with involving state-machines to evaluate their effect on the proposed hardware design. The experimental and synthesis results show that the two methods, supporting all five transform types, require less than 3% of the offered FPGA device area and provide respectively 318 MHz and 285 MHz as maximum operation frequency. With adding the pipelining operation, the proposed designs can support real time coding of 4Kp30 and 2Kp60 videos, respectively. Moreover, the implementation based on state-machines offers about 45% operations number and hardware area reduction.