Simplicity versus accuracy in a model of cache coherency overhead

The important factors building a model of coherency overhead for a single-bus, shared memory multiprocessor are analyzed. Three architectural features are examined: the size of the coherency block, the cache size, and the type of bus operation used to carry out a particular coherency function. The experiments judge the effect of each architectural parameter on model accuracy by selectively including it in a base model and then comparing the model's predictions of coherency overhead to the results of detailed multiprocessor simulations. The results indicate that coherency block size is critical to include in a model of coherency overhead. This improves the accuracy of the base model by a factor of approximately 5-50, depending on the application. Cache size and the type of coherency-related bus operation are less important, contributing a 1.5% (for 128 kbyte caches) and 6% improvement, respectively, averaged over all traces.<
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