Dual loop clock duty cycle corrector for high speed serial interface

A mixed mode Duty Cycle Corrector (DCC) with dual loop feedback for high frequency clock is proposed in this work. The proposed DCC adjusts the duty cycle of input clock by varying its rise time and fall time. The duty cycle adjuster is vital component of the circuit, which works on the principle of adjusting the pull up and pull down strength of the inverter via fed back digital signals. This circuit uses two stages of correction with first stage doing coarse correction and second stage doing fine correction. DCC is simulated in SPICE using Cadence Virtuoso in CMOS process with latest technology. The proposed DCC corrects the duty cycle of clock in the frequency range 4 to 8 GHz. The output duty cycle accuracy is 50±1% and the input duty cycle range is from 40% to 60%. It operates with a supply voltage of 1 V and dissipates 5.8 mW power at 8 GHz. The peak to peak jitter is 1.61 ps at 8 GHz. The proposed DCC is insensitive to PVT variations.