A process and temperature insensitive CMOS linear TIA for 100 Gbps/λ PAM-4 optical links

A linear TIA for a 53 GBd PAM-4 optical link to support 100 Gbps data rate on a single wavelength is reported. Designed in a 16 nm FinFET CMOS process, the chip consumes 61 mW with <; 2 % THD at 600 mVpp differential output swing, 27 GHz bandwidth, and an input referred noise density of 18.3 pA/√Hz. Transimpedance can be programmed from 63 to 80 dBΩ in 0.5 dBΩ steps. Dynamic voltage scaling tightly controls the bandwidth and in-band peaking across PVT variations to improve the parametric yield.