A new mechanism of signal path charging damage across separated power domain deep N-Well interface

In this paper, a new mechanism of signal path charging damage is observed across a separated power domain interface from the non-DNW (Deep N-Well) to DNW region. This damage mechanism is unlike the damage outside DNW from the DNW to non-DNW region unveiled in our previous work. It is found that damage takes place inside the DNW and both NMOS and PMOS transistors are impacted instead of NMOS only. A model for the damage mechanism is proposed and verified comprehensively using test patterns in a 40nm logic process combined with SPICE simulations. Several protection schemes are proposed to avoid this new mechanism of charging damage.