An Ultra-low Power System On Chip Enabling DVS with SR Level Shifting Latches

This paper presents an ultra-low power flexible on-chip bus with SR level shifting latches to enable fine grained dynamic voltage scaling (DVS) in self-powered systems. This approach allows Ultra-low Power (ULP) systems-on-chip (SoC) to operate in three modes depending on the available energy and harvesting conditions. The proposed SR latch overcomes the area and power limitations of conventional level shifters to allow each block in the system to operate at either its minimum energy or minimum power point. The proposed latch can also level shift up or down allowing users to tune the voltage of each block post fabrication. A test SoC with the proposed SR latches was fabricated in commercial 130nm technology and measured results are reported. The proposed approach allows an average of 45.2% reduction in active power compared to a reference state-of-the-art ULP SoC when operated at 32KHz. An additional 87% savings can be achieved when operating each sub-block at its minimum voltage.