A 100nW 10-bit 400S/s SAR ADC for ultra low-power bio-sensing applications

This paper presents a successive approximation analog-to-digital converter (SAR ADC), which uses an operating scheme that relaxes significantly the requirements for the sampling switches. The method consists on running the ADC with an eight times faster clock and executing the analog data processing on 1/8
^th
of the available time. During 7/8
^ths
of the conversion period, the ADC is tracking the input signal. This technique highly diminishes the constraints for the on and off resistances of the sampling switches, and is particularly suited for low-speed SAR ADCs, which are used in wearable technology for acquiring bioelectrical signals such as electroencephalograms. We have implemented a 10-bit ADC in a 0.18 μm CMOS process, applying this operating method, and achieving an ENOB of 9.6-bit at approximately the Nyquist frequency. It consumes 100 nW from a 1.2 V supply, and has a figure-of-merit of 320 fJ/conv.