Design and Characterization of a Low-Noise Front-End Readout ASIC in 0.18- $\mu$ m CMOS Technology for CZT/Si-PIN Detectors

In this paper, we report the recent development of a low-noise front-end readout application-specified integrated circuit (ASIC) for cadmium–zinc–telluride (CZT) and Si-p-i-n detectors. The readout chain consists of a charge sensitive amplifier, a CR–RC pulse shaper followed by a Sallen–Key low-pass filter, readout buffers, and a discriminator. The layout using deep n-well (DNW) is adopted to optimize the noise performance. A prototype ASIC is implemented in TSMC CMOS 0.18-
$\mu \text{m}$
, 1.8 V/3.3 V mixed-signal technology. The die size of the prototype chip is 2.1 mm
$\times$
2.5 mm. At room temperature, the equivalent noise charge of the front-end readout channel using DNW implementation is 112 e
⁻
(rms) + 17 e
⁻
pF at the power consumption of less than 2 mW/channel. The linearity error is less than 3%. By connecting the readout ASIC to a CZT detector, we obtained that the energy resolutions of a
$\gamma$
-ray spectrum are 3.9% and 5.5% (full-width at half-maximum), respectively, at the 59.5-keV line of
²⁴¹
Am source. The ASIC is a good solution of front-end electronics for personal dosimeters.