Design of an error detector circuit for BPSK costas loop for carrier synchronization in millimeter-wave receivers

This paper presents the system requirements for the implementation of an error detector in Costas Loops for carrier synchronization in millimeter-wave receivers. When the inputs to a circuit are baseband signals, there is a need for DC coupling, four-quadrant operation and linear processing on the signals. Based on the system requirements, a wideband DC coupled, four quadrant analog multiplier circuit was designed to realize an error detector in Costas Loop. The chip was designed in 130nm SiGe:BiCMOS HBT technology with ft of 250 GHz and fmax of 300 GHz. The error detector circuit consumes a total DC power of 160 mW.