Pulse forming network with optimized pulse power and rise time

This paper presents simulation and hardware implementation of a Pulse Forming Network (PFN) which is optimized for pulse power and rise time. In the topology used pulse forming network consist of a ladder L-C network with low resistance path for the charging and discharging of capacitors. The PSpice software has been used to confirm the performance accuracy of the method. The simulation result is presented for 20kV charging voltage for single stage, ten sections PFN. A 10MW pulse is obtained for 5μ pulse width and 350ns rise time. The experimental setup of the circuit is developed for five section single stage to generate 250W pulse power.