A 16Gb LPDDR4X SDRAM with an NBTI-tolerant circuit solution, an SWD PMOS GIDL reduction technique, an adaptive gear-down scheme and a metastable-free DQS aligner in a 10nm class DRAM process

High-density and high-speed DRAM requirements have been ever-increasing to achieve a better user experience for mobile systems, by adopting QHD (2560×1440), and higher display resolutions, dual cameras, augmented reality, and advanced driver-assistance systems. LPDDR4X has been the hand-held and mobile memory of choice due to its high speed (5.0Gb/s/pin [1]) and low-power data retention (<0.1mW/Gb [2-3]), as well as reliability due to in-DRAM ECC. The DRAM process continues to scale down to the 10nm era to meet the ever increasing density requirements (LPDDR4X density doubles every two years for flagship smart-phones). However, poor data retention characteristics due to smaller storage capacitances and device issues, such as reliability (NBTI) and leakage (especially core transistors), with the traditional poly-gate and planarbulk technology becomes a primary concern for mobile DRAM. In-DRAM ECC is fully supported by the JEDEC LPDDR4 specification by the introduction of the new masked-write command (MWR; f
CCDMW
=32f
CK
), however the area overhead (6.25%), due to the additional parity arrays for a (136, 128) single-error-correction code [4], is currently limiting for mass production in terms of chip cost. This overhead can be mitigated by adopting a scaled technology node that enables a smaller chip size as well as better retention time due to ECC. This paper presents several circuit techniques to maintain LPDDR4X's high speed and low power in a 10nm class process, thereby enabling a cost-effective DRAM design with inDRAM ECC: using (1) an NBTI-tolerant circuit solution that covers whole high-speed circuit regions, (2) a sub-WL driver (SWD) PMOS GIDL-reduction technique ensures stable power recovery, (3) an adaptive IO buffer current gear-down scheme based on user-scenarios, and (4) a metastable-free DQS aligner. Figure 12.2.1 shows the top-level block diagram of the 8Gb/1channel macro, with an in-DRAM ECC using a (136, 128) single-error-correction code, similar to that of previous 20nm designs [2-4].