A 1.1μm-Pitch 13.5Mpixel 3D-stacked CMOS image sensor featuring 230fps full-high-definition and 514fps high-definition videos by reading 2 or 3 rows simultaneously using a column-switching matrix

Slow-motion video is a desirable feature for state-of-art smartphones. The effect is achieved by capturing a video at a higher frame rate and playing it back at a lower frame rate. While the still-image resolution of smartphone cameras ranges from 8MP to 25MP, standard videos are limited to 3 formats: 3840×2160 (4K2K, 2160p), 1920×1080 (Full High Definition, FHD, 1080p), and 1280×720 (High Definition, HD, 720p). CMOS image sensors using various column-parallel aDc architectures have been reported to reach high frame rates [1-5]. The single-slope (SS) ADC is an attractive choice for a balanced performance among high speed, low noise, small area, and low power consumption. However, in conventional SS ADC design, each ADC is hardwired to a column signal line. ADCs for skipped columns are left idle during the subsampling operation, and the potential to reach higher frame rate is not optimized. In this paper, we develop an approach in which all the column ADCs are fully utilized in both of the 2-to-1 and 3-to-1 subsampling modes, such that the maximum of 4x faster FHD and 9x faster HD videos are demonstrated with reference to the 1-to-1 non-subsampled 4K2K video.