Hardware/software co-simulation of entropy coder for compressive sensing based scalable video codec system

Due to the immense volume of data generated, there is a growing demand for low-complexity and low-power video compression algorithms for encoding the sequentially captured data frames. This paper first introduces Compressive Sensing based Scalable Video Coding (CS-SVC) for efficient on-board compression at the transmitter end. The objective is to partition the CS-SVC system and allocate different system blocks on the available hardware/software resources in a Zynq 7000 All Programmable System-on-Chip (SoC) for deriving a high throughput co-design. The simulation and profiling of the CS-SVC system are analyzed on MATLAB platform. The hardware/software partitioning of the CS-SVC system blocks based on the result of profiling is discussed next. The computationally intensive regular tasks are implemented in the hardware accelerators, whereas the other procedures of CS-SVC system such as Zig-zag scanning, entropy coding are executed by the ARM processor for performance improvement. In the current work, the entropy coder block is simulated and implemented on Vivado platform for programming the Processing System in Zynq 7000 SoC.