Fault Modeling and Parallel Testing for 1T1M Memory Array

Memristor memory is a novel electrical device, which has attracted more and more attentions as a new nonvolatile memory due to its fast write/read speed, low operation voltage, long data retention time, and excellent scalability. The gateless 1 memristor (1M) crossbar memristor structure has the highest density but suffers from the sneak-path problem. One transistor and one memristor (1T1M) structure can eliminate the effect of sneak-path currents. However, leakage currents exist in the 1T1M memory array through the
off
transistors, which will affect the write and read operations. The wire resistance which is inevitable in the memristor circuits is another fatal factor that affects the write and read operations. In this paper, we analyze the effect of the leakage currents and wire resistance during the write and read operations based on 1T1M memory array under different array sizes. Memristor can be employed as either logic gate or memory element. Stateful logic operations can be performed through memristors and resistors with the help of appropriate circuit. In this paper, a parallel testing method was proposed based on memristive stateful logic which can improve the test efficiency compared to the traditional March algorithm. The proposed parallel testing method is 1.242 times faster than the March algorithm when the array size is 64 * 64, and when the array size increased to 1024 * 1024, the parallel testing is 1.249 times faster than the March algorithm while the test time can be reduced by 19.51% and 19.92%, respectively.