Analysis of the settling behavior of an external reference voltage source for a 16 bit and 200MS/s pipeline analog-to-digital converter

High-Performance Analog to Digital Converter (ADC) have high requirements concerning the reference voltage source. In a small period of time the reference voltage has to settle with a high accuracy. Otherwise the linearity of the ADC degrades. In this paper the settling of an external reference voltage source is examined. Therefore optimization techniques for the signal path of the reference voltage are presented. This includes methods for reducing the external parasitic inductance as well as design techniques for an enhanced settling curve. Under typical conditions, the achieved reference voltage source settles with an accuracy of 15 μV in less than halve a clock cycle for a 200MS/s and 16 bits Pipeline ADC.