Application specific design for digital beam-former (DBF)

This paper aim at designing and implementing a Digital Beam-Former (DBF) using Verilog software. This paper presents a survey of DBF design, with intended solution to perform the design on VHSIC Hardware Description Language (VHDL). First, a Matlab simulation of the indented solution of DBF, is presented. Then, a Verilog language is built to design the solution of DBF, simulated using ModelSim, and synthesized using Synopsis tools. The synthesis was implemented using 65 nm technology and it reports a 324.9 μW when operating at 10 MHz. Hence, the DBF system is implemented to run under lower power constraints.