Design and performance analysis of modified unsigned braun and signed Baugh-Wooley multiplier

Adders and Multipliers play a vital role in the functioning of various systems used in communication and signal processing. Baugh Wooley and Braun multipliers employ parallel architecture and hence they are the most frequently used multipliers for signed and unsigned operations. In any system design, the three main constraints which determine the performance of the system are speed, area and power requirement. This work involves design and implementation of modified Baugh-Wooley and Braun multipliers for signed and unsigned number multiplication respectively and analysis with respect to speed and power consumption of the designed multipliers. The adder is designed using three different logics, namely, Basic CMOS, Domino and Split Path Data Driven Dynamic Logic (SPD3L). The designed adder is then used to construct the multipliers. An improvement in power and reduction in delay is observed for both the designed multipliers.