Designing a level shifter to enhance the performance suitable for low power applications

This paper enhances the performance level of a level shifter for low power applications. It presents a power efficient level shifter circuit which converts low level input voltages into high output voltages. A fast and power efficient level shifter circuit is proposed. Here the efficiency of both pull up and pull down transistors is improved. The proposed circuit is demonstrated using 180 nm technology and various parameters and design rules are obtained. In order to have a fair comparison between the structures, a unit buffer and an inverter are added as the load circuit and input buffer respectively. The power consumption of the proposed circuit is a function of size of capacitive load. The power consumption increases as the size of the load increases.