Aging resilient RO PUF with increased reliability in FPGA

Several design approaches have been proposed for IP protection, attestation, etc. of FPGA hardware designs and physical unclonable function (PUF) is one of the most popular amongst them. However, different transient variations like temperature, supply voltage and environmental noise make it challenging for a PUF to produce a reliable signature. Besides the above-mentioned issues that impact the transient reliability of PUFs, aging is another factor that produces irreversible impact on the reliability of PUFs. Though an aging resistant ring oscillator (RO) PUF has been proposed previously for ASIC design, implementing the same technique in FPGA is impossible as it involves redesigning the circuit at transistor level. In this paper, we propose an aging resilient RO PUF design on FPGA that exploits the SRAM cells and multiple paths available in FPGA look up tables (LUTs). The aging of our proposed RO PUF can be slowed down by putting the oscillation path into sleep mode. Experimental measurements from Spartan 3A FPGA boards demonstrate that our proposed RO PUF is less affected by aging, the reliability of which increases by 37.4% on an average. Moreover, by comparing our design with conventional RO PUF in FPGA, the aging degradation decreases by 37%.