A 6-bit 1.3-GS/s Ping-Pong Domino-SAR ADC in 55-nm CMOS

This brief presents a 6-bit domino successive approximation register (SAR) analog-to-digital converter (ADC). The proposed domino-SAR ADC architecture provides high-speed domino operation and the offset immunity of SAR ADCs. The ping-pong operation enacts a master clock sampling scheme to achieve a sampling rate of 1.3 GHz. A prototype ADC chip was fabricated using a 55-nm CMOS technology. The chip consumes a total power of 3.5 mW from a 1.2-V power supply. The measured peak SNDR and SFDR are 33 and 48 dB, respectively. The peak effective number of bits is 5.2 bits, equivalent to the figure of merit of 73 fJ/conversion step.