Challenges of ultra-thin WLCSP

While the applications of consumer electronics are trending to with slim and stylish outlook, the space is extremely constraint within the electronic devices. WLCSP enables low profile, small form factor and relatively easy assembly process, it is perfect to meet those space constrains. However, for ultra-thin WLCSP, reduced wafer thickness would increase the risk of warpage and crack during the processing. When the silicon of WLCSP is ultra-thin (less than 200um), its mechanical strength is low, its handling post wafer lapping process is one of the major challenges. The crack risk is even higher when the wafer is big (12”) and with brittle ELK layer. The other challenge is wafer warpage, which is from the CTE miss-match between silicon and passivation polymer. Therefore, in order to diminish the wafer warpage and crack risk, experiments are performed to conduct for the risk mitigation, including laser grooving process optimization, dicing tooling selection and recipe optimization study. In this study, a test vehicle with 170um Silicon thickness was evaluated. Screen and corner DOEs which includes laser grooving conditions and dicing conditions were performed to come out the tooling selection and process windows. Finally, functional test and reliability test are all passed. This ultra-thin WLCSP has been proved to apply to the consumer electrics products.