A Low-Latency and Area-Efficient Gram–Schmidt-Based QRD Architecture for MIMO Receiver

Despite a low algorithmic complexity, Gram-Schmidt (GS) method has not been widely employed in the dedicated hardware architecture of matrix decomposition due to its expensive square-root and division operations. This paper presents a low-latency and area-efficient QR decomposition (QRD) architecture based on the modified GS method. The low complexity architecture is enabled by efficiently substituting the square roots and divisions with coordinate rotation digital computer (CORDIC) operations. In the proposed architecture, when implementing the division by the results of square root, the key design point is that the rotation directions of CORDIC are shared between vectoring and rotation modes using the orthogonality of the CORDIC rotation matrix. As a result, the division operation can be performed with the assistance of square root, leading to the hardware cost reduction. The overhead of scaling factor compensation has also been reduced with pre-scaling. The proposed low complexity scheme can be implemented in the semipipelined and iterative architectures for high throughput and small area applications, respectively. Hardware implementation results with 65-nm CMOS process show that the proposed semipipelined architecture achieves 17% and 141% improvement of normalized hardware efficiency in QRD and projection operations, respectively, compared with the conventional approaches.