Low-Power Single-Ended SAR ADC Using Symmetrical DAC Switching for Image Sensors With Passive CDS and PGA Technique

An integrated, power-saving SAR analog-to-digital converter suitable for image sensor applications is presented in this paper. In comparison with previous works, the proposed, build-in passive correlated double sampling (CDS) and programmable gain amplifying (PGA) technique is superior in power, as it achieves correlated noise cancellation and signal amplification without additional OTAs. Furthermore, inspite of a single-ended signal from the image sensor array, single-endedto-differential sampling is used to enable symmetrical DAC switching. The adopted LSB-first algorithm, utilizing the strong correlation between neighboring pixels, significantly reduces the energy and number of bitcycles per conversion. Additionally, a comparator with four inputs is adopted to keep the DAC array unchanged, avoiding power consumption from the operation of the initial guess for next quantization. Fabricated using a 65-nm process, the 10-bit ADC occupies a die area of 0.19 mm2. The measured DNL and INL are less than +0.68/-0.45 LSB and +1.07/-1.15 LSB, respectively. Operating at 40 MS/s, the ADC provides an SNDR of 55.7 dB and SFDR of 70.9 dB for signal bandwidths of 17.2876 MHz and consumes 415.2 μW from a 1.2-V power supply, resulting in a figure of merit of 21.7 fJ/conversion-step. Additionally, the CDS and PGA functionality are verified to be effective in removing reset level influence and providing gains of -6 dB, 0 dB, and 6 dB.