Reverse-bias stability and reliability of hole-barrier-free E-mode LPCVD-SiNx/GaN MIS-FETs

With substantially limited holes generation, the E-mode n-channel LPCVD-SiNx/GaN MIS-FET delivers small NBTI (with V
_ds
= 0 V and a negative V
_gs
= -30 V) even without a hole-barrier. In high reverse-bias (i.e. high drain bias off-state with V
_gs
<; V
_th
and large V
_ds
) stress, larger negative gate-bias is found to accelerate positive shift in V
_th
, suggesting a hole-induced gate dielectric degradation mechanism. It is also revealed that the hole-induced dielectric breakdown can be greatly contained when V
_gs
is limited to a few volts below V
_th
.