Hysteresis-free negative capacitance germanium CMOS FinFETs with Bi-directional Sub-60 mV/dec

In this paper, we report on the first hysteresis-free Ge CMOS FinFETs exhibiting sub-60 mV/dec subthreshold slope (SS) in both forward and reverse sweeps at room temperature. Minimum SS
_rev
of 7 mV/dec and SSfor of 17 mV/dec with a large voltage hysteresis of -4.3 V are achieved on 10 nm Hf
_0.5
Zr
_0.5
O
₂
(HZO) Ge pFinFET. Ferroelectric (FE) HZO film is integrated with Al
₂
O
₃
/GeOx as a gate stack. Recessed source/drain and fin-channel process scheme is implemented to yield such sub-60 mV/dec 3D devices. With scaled HZO thickness down to 2 nm, Ge pFinFET and nFinFET show SS (forward/reverse) of 56/41 and 43/49 mV/dec respectively. Negligible voltage hysteresis is obtained with -4 mV for pFinFET and 17 mV for nFinFET.