Single bit-line low power 9T static random access memory

The Static random access memory (SRAM) design is demanding due to the variation of the process parameters with CMOS technology scaling. It becomes challenging because the stability, write ability and leakage power consumption should all be considered to provide an optimum performance. The proposed cell consumes 8.54% less power compared to double bit-line SRAM. The 2 bit-line scheme of SRAM has more dissipation of power due to the charging and discharging of complementary bit lines. This paper puts forth a single bit-line 9T SRAM design which consumes lower power and low leakage. It has a high read SNM with good static and dynamic read/write performance. Single bit-line approach leads to lower power consumption compared to the conventional 2 bit-line SRAMs. However, the access time for read and write operation is increased.