Design of fault injection technique for VLSI digital circuits

Development of VLSI technology has increased the design complexity on the IC chip. With this, the possibility of fault occurrence also has increased. In many of the mission critical applications, the reliability of the system is given a higher priority. In order to make a system reliable, fault tolerant techniques are included in most of the systems. Fault injection is an essential part of the fault tolerant system design. It includes processes of fault insertion and observation of system behaviour in presence of inserted faults. In this paper, an efficient fault injection method is proposed which aims at covering all possible fault occurrences with increased speed of fault injection. This method is applied for s27 circuit and Maximally Redundant signed Digit (MRSD) adder. The proposed technique is implemented using Xilinx 14.5 ISE tool.