Design and implementation of low power mitchell algorithm based logarithmic multiplier

Multiplication is a significant operation in signal processing but slow and complex leading to high power consumption and area. Digital Signal Processing repetitively uses multiplication to carry out computations. One feasible solution to simplify multiplication is to use Logarithmic Number System (LNS) instead on Binary. LNS method greatly reduces the computation time but with a trade-off in accuracy. However, we can use this approach in DSP in which speedy computation is of greater concern than accuracy. This paper presents a low power logarithmic multiplication approach aimed to achieve faster computation. The hardware implementation involves very primitive components like adder, shifter and counter which consume less power. Further, adiabatic logic is used at circuit level to reduce power consumption. Power analysis is carried out for traditional CMOS logic and Adiabatic logic using Cadence Virtuoso. The proposed fully adiabatic Switch Rail Charge Recovery Logic (SCRL) and quasi adiabatic Efficient Charge Recovery Logic (ECRL) based logarithmic multiplier is proved to reduce power dissipation by a factor of 81.36 % and 33.4 % respectively than CMOS implementation.