Dependence of ${V}_{\text {TH}}$ Stability on Gate-Bias Under Reverse-Bias Stress in E-mode GaN MIS-FET

In this letter, we investigated the threshold voltage V
_TH
stability under reverse-bias step-stress in the E-mode LPCVD-SiNx/PECVD-SiNx/GaN MIS-FET. Under the OFF-state reverse-bias stress with the same net gate-todrain voltage (VGD), the V
_TH
shift shows an obvious dependence on the negative gate bias. With a V
_GS
of 0 V, the V
_TH
shift is small and recoverable, while the V
_TH
shifts are substantially larger with more negative gate bias (V
_GS
= -20 V). This larger V
_TH
shifts caused by the negative V
_GS
can be explained with a hole-induced degradation model. An important indication revealed by this model is that negative gate bias should be well confined in high-power switching applications of GaN E-mode MIS-FET for a stable V
_TH
.