Stochastic flash ADC considering comparator metastability implemented in FPGA

This paper deals with the implementation of a stochastic flash ADC with the presence of comparator metastability, in a field-programmable gate array. Stochastic flash ADC exploits comparator threshold variation and can be implemented with simple and highly digital structures. We show that such designs is also prone to comparator metastability, therefore we propose an averaging scheme as a simple means to handle the situation. Experimental results from a prototype system based on an FPGA is given which shows the effectiveness of the averaging technique, resulting in a maximum measured SNDR of 22.24 dB with a sampling rate of 98 kHz.