FPGA-based SDR implementation for FMCW maritime surveillance radar

This paper presents an overview of FPGA-based SDR implementation on FMCW X-band maritime surveillance radar INDERA MX-4. The FPGA implementation proposed in this work significantly simplifies the hardware architecture of the radar. In particular, the RF and electronic systems can be simplified into 3 main units only, i.e. LO, FPGA (with integrated ADC) and transceiver. Such architecture simplification should lead to more compact and robust RF and electronic system hardware. The FPGA development is carried out on FPGA development board ALTERA Stratix III following standard FPGA programming steps. The radar functionalities programmed in the FPGA unit include DSP, mixers, frequency agility, RTDC and ADC, and have been successfully verified. The developed FPGA unit has been integrated with the rest of the radar subsystems (antennas, transceiver, RF unit, etc.) to realize an FPGA-based SDR. Field measurements, located at the harbor of Merak in Java, Indonesia, have been carried out to verify the developed FPGA-based SDR. It has been demonstrated that the FPGA unit has worked properly to support the designed SDR implementation on the radar. In particular, good detection of various ships in the harbor area has been achieved. This result demonstrates the successful implementation of the FPGA unit in the complete integrated SDR system.