A harmonic-free cell-based all-digital delay-locked loop for die-to-die clock synchronization of 3-D IC

A wide-range and harmonic-free cell-based all-digital delay-locked loop (ADDLL) is proposed for die-to-die clock synchronization of three-dimensional integrated circuits (3-D ICs). The proposed ADDLL can tolerate delay variations between through silicon vias (TSVs) and synchronize the clock signals between vertically stacked dies of a given 3-D IC. It uses resettable digital-controlled delay lines (DCDLs) to solve the harmonic-locking problem, and adopts successive approximation register-controlled (SAR) scheme to shorten the lock process. Designed in 65nm CMOS low power standard cell library, the total layout active area is 133μm×133μm. The simulation results show that the operating frequency is from 112MHz to 1.5GHz, the lock time is constant 62 cycles of the input clock, and the power consumption is estimated to be 1.1mW at 1.2V supply voltage and 1.5GHz clock frequency.