A survey of recent contributions on low power NoC architectures

The Network-on-Chip (NoC) paradigm has been herald as the solution to the communication limitation that System-On-Chip (SoC) poses. However, power Consumption is one of its major defects. To ensure that a high performance architecture is constructed, analyzing how power can be reduced in each area of the network is essential. Power dissipation can be reduced by making adjustments to the elements in routers. The architecture itself and the Links. This paper will entail a survey conducted on recent contributions on NoC. As well as the techniques employed by researchers towards the reduction of power in the router architecture, network architecture and the links.