Shallow source/drain extension effects on external resistance in sub-0.1 /spl mu/m MOSFETs

Accurate external resistance extraction for shallow source/drain extension (SDE) MOSFET's is demonstrated using a unified mobility model for inversion and accumulation layers. The parasitic resistance in the accumulation layer (R/sub acc/) is highly dependent both on the SDE junction depth (X/sub j/) and the gate overlap length (L/sub ou/). Due to the laterally finite doping gradient, R/sub acc/ becomes dominant among other external resistance components in sub-0.1 /spl mu/m MOSFETs. Hence, device optimization to minimize R/sub acc/ is necessary in order to improve on-current and SDE to the gate coupling. A NMOS transistor with L/sub eff/ of 0.08 /spl mu/m shows a maximum on-current while maintaining a lower off-leakage current for a L/sub ou/ of 20 nm and X/sub j/ of 40 nm.