Interfacial electronic traps in surface controlled transistors

Carrier recombination at interfacial electronic traps under a surface controlling gate electrode is analyzed using the Shockley-Reed-Hall steady-state recombination kinetics to provide a theoretical basis for quantifying the direct-current current-voltage (DCIV) method for monitoring and diagnosis of MOS transistor reliability, design, and manufacturing processes. Analytical expressions for DCIV lineshape, linewidth, peak gate-voltage and peak amplitude are derived for the determination of interface trap densities, energy level, and spatial location. DCIV peaks in the intrinsic to flat band gate-voltage range originate from carrier recombination at interface traps located over the channel region. Additional peaks in the surface accumulation gate-voltage range originate from interface traps covering the gated p-n-junction space-charge region. Effects on the DCIV line shape from minority carrier injection level and diffusion are described. Examples are given for the determination of the quantum density of states of process-residual interface traps of unstressed MOS transistors as well as hot-carrier-generated interface traps of stressed MOS transistors.