Memory Physical Aware Multi-Level Fault Diagnosis Flow

Advanced methods of fault detection and diagnosis become increasingly important for the improvement of reliability, safety and efficiency in nanoscale designs. Because the existing approaches do not give a deeper insight and usually do not allow a comprehensive fault diagnosis, multi-level model based methods of fault detection were developed by using hierarchy of detection and diagnosis methods. This contribution proposes a memory physical (scrambling) aware multi-level fault diagnosis flow which is generic and applicable both for planar- and FinFET-based memories. In addition, special test algorithms for classification of static and dynamic faults are discussed while for classification of FinFET-specific faults a new test algorithm March FFDD is proposed. The flow is validated on 16nm FPGA board as well as it has been applied to numerous chips enabling successful physical failure analysis (PFA). At the end of the paper some real-life case scenarios of the flow application are presented.