Performance analysis for Vedic multiplier using modified full adders

Area efficient architecture is today's major concern in the field of VLSI, Digital signal processing circuits, cryptographic algorithms, wireless communications and Internet of Things (IOT). Majority of the architectures use multiplication. Realization of multiplication by using repetitive addition and shift and add methods consumes more area, power and delay. Vedic is one of the efficient multipliers. Design of Vedic multiplier using different sutras reduces area and power. From the structure of Vedic multiplier, it is clearly observed that there is scope to design an efficient architecture. In this research, Vedic multiplier is designed using modified full adder which consumes less number of LUT's, slices and delay when compared to normal conventional Vedic multiplier. Simulation and synthesis are carried on XILINX ISE 12.2 software. FPGA results of the proposed multiplier show that number of LUT's is less by 13.8% in the modified Vedic Multiplier (4×4) and less by 7.5% in modified Vedic Multiplier(8×8). Delay is less by 10% in modified Vedic Multiplier (4×4) and 7.2 % in modified Vedic Multiplier (8×8).