Dependable system design with soft error mitigation techniques in SRAM based FPGAs

Radiation effects are one of the major challenges facing the designers and developers while implementing dependable systems in SRAM based FPGAs. Soft errors can occur in logic resources, routing resources, I/Os, BRAMs, virtually any part of the FPGA. Error mitigation techniques are necessary to ensure the dependability of the implemented designs. Moreover, to check the efficiency of the mitigation techniques implemented are important. This paper suggests a design flow for verification and validation of fault tolerant techniques which is based on error injection in the logic design by VHDL code modification. TMR and DWC techniques are chosen for the analysis purpose. Verification is performed by simulation-based fault injection and validated by emulation. The ChipScope Pro analyzer is used for emulation analysis. This paper proposes the error recovery mechanism based on SECDED which can mask a single error and can detect double errors in the FPGA memories. To achieve proper information on the efficiency of soft error mitigation technique, the device has to be exposed to radiation sources. This paper also proposes an irradiation experimental setup to validate the feasibility and efficiency of the mitigation techniques for dependable system developments in FPGAs.