Metastability investigation in adiabatic logic for wake-up receivers: Critical concerns in the JK-FF of a CPAL binary counter

Low power wireless communication is essential for the realization of IoT devices connected because radio transceivers are one of the biggest sources of power drains. The low power Wake-up Receiver (WUR) is a promising technology that can facilitate this by enabling an on-demand and asynchronous wake-up signal. Although the concept of WUR is not new, only recently it has attracted significant attention from industries due to the development of IoT and energy efficiency that has become a design concern in high performance devices. On the other side, there is a strong effort on the minimization of energy consumption and dissipation associated to the analog and digital circuitry. Therefore, the strategy of AC-clocked power supply follows this tendency. In this work, CPAL JK flip-flops are evaluated regarding time violation, either for frequency shifting or phase shifting, considering the evaluate/hold state of the four-phase power-clock.