A novel approach to simulate the effect of optical proximity on MOSFET parametric yield

A simulation procedure to quantify the effect of process variations of mask making and photolithography on MOSFET performance and parametric yield is proposed. Dense layout of 0.16 /spl mu/m six-transistor SRAM cell was used. Firstly, the accuracy of optical proximity correction (OPC) of gate layout was verified by two-step simulation of mask and photoresist pattern. This was followed by the extraction of channel length dependent MOSFET drive current for the different OPC serif and misalignment options within the corresponding process latitudes. Finally, parametric yield was simulated based on statistical distributions of MOSFET parameters.