Integration of high-Q inductors in a latch-up resistant CMOS technology

Inductors fabricated using CMOS technologies based on epi/p/sup +/ substrates are severely degraded because of eddy current losses in the substrate. We propose and demonstrate a modified substrate structure, which addresses the conflicting goals of high inductor quality-factor and high latch-up immunity. Results include fabricated inductors with Q-factor as high as 16.