A 0.13 /spl mu/m CMOS technology integrating high-speed and low-power/high-density devices with two different well/channel structures

In this paper, we report a high performance 1.5 V operation 0.13-/spl mu/m gate length CMOS technology that integrates a high-speed MOSFET and a low-power/high-density one. The high-speed transistor has a superior drive-current of 700 /spl mu/A/300 /spl mu/A at an off-current of 1 nA//spl mu/m, and an extremely low junction capacitance comparable to SOI devices by utilizing a single-well/local channel structure. Obtained propagation delay for inverter gate is less than 15 ps with F/O of 1. The low-power/high density CMOS features a low standby current of 1 pA//spl mu/m, and a very narrow n/sup +/ to p/sup +/ spacing of 0.4 /spl mu/m by using a twin-well structure. This technology contains a SRAM with 3.99-/spl mu/m/sup 2/ 6-T cell or 1.9-/spl mu/m/sup 2/ load-less 4-T cell.