Thermal modeling and experimental verification using large-sized stacked chips

This paper introduces a thermal design method for 3D integration, using stacked thermal chips consisting of 100 polysilicon heaters in a 30 mm by 30 mm area on each chip to verify thermal models. For each heater, two levels of thermal load can be selected. Thermal effects from hot-spots in stacked chips were measured and verified in simulation results. Through this investigation, thermal models with a cooling plate were established. The resulting thermal design simulations can be applied to different conditions by varying both the power map of stacked chips and the flow rate of coolant supply toward an optimized operation point.