A BIST design methodology experiment

The author describes an experiment in which built-in self-test (BIST) was added to existing gate-array probe designs and simulation was used to easily identify controllability and visibility problems. He documents investigations of ECL (emitter coupled logic) gate arrays to study the advantages and costs of using BIST. The first goal of this experiment was to develop a set of rules or a design methodology that would make it possible to implement these BIST test cases without undue effort. The second was to measure the effectiveness of BIST by fault simulation. The third was to document the cost in power, pins, gates, and computer resources in the design environment. Three test case designs were chosen for this experiment such that the results would be as representative as possible.<
>