Investigation of Cycling-Induced Dummy Cell Disturbance in 3D NAND Flash Memory

The disturbance mechanism of dummy cell during memory cell cycling has been investigated in 3D NAND flash. Edge dummy cell (DMY) threshold voltage increasing was observed during cell program and erase cycling, which leads to a reduced string current and read failure. According to experiment and TCAD analysis, two mechanisms were identified to contribute to the dummy disturbance: one is the tunneling of electrons from the adjacent gate to the trapping layer during cell erase condition, which was also observed in 2D NAND; the other one is the lateral charge spreading from the trapping layer of edge cell to DMY, which is a new observation for the junction-less 3D NAND with continuous nitride trapping layer. Furthermore, an optimal DMY bias scheme under erase operation is demonstrated to suppress the disturbance.