FPGA implementation of a modified turbo product code decoder

This paper simplifies the chase decoding algorithm for TPC codes for a particular modulation scheme (BPSK). Without reducing the decoding performance, the multiplication of the new algorithm is 33% of the original algorithm. The access algorithm of receiving matrix [R] is also optimized, and the access time of receiving matrix [R] is reduced to 3%. Finally, the 800M bps TPC decoder was implemented on the xilinx xc7a200t platform.