Multiphase clock based vernier TDC on FPGA for on-chip temperature measurement application

This paper presents a high resolution Vernier Time to Digital Converter(TDC) implemented on low cost FPGA. A novel way to utilize PLLs present within FPGA presented here. The technique includes generating multiphase clocks and selecting one among them to minimize the error. With this the maximum error is 1/4 T
_CLK
rather than T
_CLK
. The BIST circuitry is also implemented to test TDC with programmable pulse generator and response monitor.