A multithreaded architecture approach to parallel DSPs for high performance image processing applications

Starting from an evaluation of recent and future image processing algorithm's properties, this paper proposes a new class of parallel DSP architectures adapting the concept of simultaneous multithreading (SMT) to signal processing applications. This concept allows to enable parallelization resources on thread level, which are unused by most recent media-professors and video-DSPs. A customizable simulator to explore the architecture's parameters dependent on algorithmic properties and implementation constraints is presented. Coarse estimations for the realization costs in terms of silicon area are derived. First simulated performance figures for selected image processing algorithms show that SMT architectures are suitable to increase the processor's overall utilization and can achieve a speed-up beyond the limits of VLIW and superscalar architectures.